hardcamlversion

RTL Hardware Design in OCaml

Hardcaml is an embedded DSL for designing and simulating hardware in OCaml. Generic hardware designs are easily expressed using features such as higher order functions, lists, maps etc. A built in simulator allows designs to be simulated within Hardcaml. Designs are converted to either Verilog or VHDL to interact with standard back end tooling.

AuthorJane Street Group, LLC <opensource@janestreet.com>
LicenseMIT
Published
Homepagehttps://github.com/janestreet/hardcaml
Issue Trackerhttps://github.com/janestreet/hardcaml/issues
Maintaineropensource@janestreet.com
Dependencies
Source [http] https://ocaml.janestreet.com/ocaml-core/v0.12/files/hardcaml-v0.12.0.tar.gz
md5=bddd766d20ca9d90d3d4d0d521e0d2b2
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Edithttps://github.com/ocaml/opam-repository/tree/master/packages/hardcaml/hardcaml.v0.12.0/opam