hardcamlversion

RTL Hardware Design in OCaml

Hardcaml is an embedded DSL for designing and simulating hardware in OCaml. Generic hardware designs are easily expressed using features such as higher order functions, lists, maps etc. A built in simulator allows designs to be simulated within Hardcaml. Designs are converted to either Verilog or VHDL to interact with standard back end tooling.

AuthorJane Street Group, LLC
LicenseMIT
Published
Homepagehttps://github.com/janestreet/hardcaml
Issue Trackerhttps://github.com/janestreet/hardcaml/issues
MaintainerJane Street developers
Availablearch != "arm32" & arch != "x86_32"
Dependencies
Source [http] https://ocaml.janestreet.com/ocaml-core/v0.15/files/hardcaml-v0.15.0.tar.gz
sha256=0dc4153de7ffa0a3471d9ecd8044f701e300290ce4c2e716187e063e8cf2f8b1
Edithttps://github.com/ocaml/opam-repository/tree/master/packages/hardcaml/hardcaml.v0.15.0/opam