ppx_hardcamlversion Documentation on ocaml.org
Rewrite OCaml records for use as Hardcaml Interfaces
An interface in Hardcaml is an OCaml record with special attributes including a bit width and RTL netlist name. Input and output ports of a hardware design can then be accessed through the OCaml record. This allows easier management of bundles of ports when working with the Simulator, Netlist generation or hierarchical designs.
| Author | Jane Street Group, LLC |
|---|---|
| License | MIT |
| Published | |
| Homepage | https://github.com/janestreet/ppx_hardcaml |
| Issue Tracker | https://github.com/janestreet/ppx_hardcaml/issues |
| Maintainer | Jane Street developers |
| Available | arch != "arm32" & arch != "x86_32" |
| Dependencies | |
| Source [http] | https://github.com/janestreet/ppx_hardcaml/archive/refs/tags/v0.17.1.tar.gz md5=74cb19720c582bd5c4559aba77807024 sha512=5179b3741e94cf603fc8907b9946a1021979463262e7ab7cbe83df0f320ed2f2bfa8d8aef5ed53f10f9fcd64aaad5f618b26ef16ecabe7bdb358cc9ff01317d7 |
| Edit | https://github.com/ocaml/opam-repository/tree/master/packages/ppx_hardcaml/ppx_hardcaml.v0.17.1/opam |
Required by
- hardcaml_axi>=v0.17.0
- hardcaml_c>=v0.17.0
- hardcaml_circuits>=v0.17.0
- hardcaml_handshake>=v0.17.0
- hardcaml_of_verilog>=v0.17.0
- hardcaml_verify>=v0.17.0
- hardcaml_verilator>=v0.17.0
- hardcaml_xilinx>=v0.17.0
- hardcaml_xilinx_reports>=v0.17.0
