hardcaml_of_verilogversion

Convert Verilog to a Hardcaml design

The opensource synthesis tool yosys is used to convert a verilog design to a JSON based netlist representation. This library can load the JSON netlist and build a hardcaml circuit.

Code can also be generated to wrap the conversion process using Hardcaml interfaces.

AuthorJane Street Group, LLC
LicenseMIT
Published
Homepagehttps://github.com/janestreet/hardcaml_of_verilog
Issue Trackerhttps://github.com/janestreet/hardcaml_of_verilog/issues
MaintainerJane Street developers
Dependencies
Source [http] https://ocaml.janestreet.com/ocaml-core/v0.16/files/hardcaml_of_verilog-v0.16.0.tar.gz
sha256=d0c73140e80b48f7e971d6fa94e7f8ed8aa64cd7685d0fb442eb590ba6a244b4
Edithttps://github.com/ocaml/opam-repository/tree/master/packages/hardcaml_of_verilog/hardcaml_of_verilog.v0.16.0/opam
No package is dependent