hardcamlversion Documentation on ocaml.org
RTL Hardware Design in OCaml
Hardcaml is an embedded DSL for designing and simulating hardware in OCaml. Generic hardware designs are easily expressed using features such as higher order functions, lists, maps etc. A built in simulator allows designs to be simulated within Hardcaml. Designs are converted to either Verilog or VHDL to interact with standard back end tooling.
Author | Jane Street Group, LLC |
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License | MIT |
Published | |
Homepage | https://github.com/janestreet/hardcaml |
Issue Tracker | https://github.com/janestreet/hardcaml/issues |
Maintainer | Jane Street developers |
Available | arch != "arm32" & arch != "x86_32" |
Dependencies |
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Source [http] | https://github.com/janestreet/hardcaml/archive/refs/tags/v0.17.1.tar.gz md5=7435ee8610c2205c5f912b4bf09163b0 sha512=38d7cf428bd3491024212e52776ac582183d7b5f6a494589a3697d9a213fa18347d6eeea23327859c340b0cb3b967c08cd21a8a7f8d15cf2de20e5598cb8456d |
Edit | https://github.com/ocaml/opam-repository/tree/master/packages/hardcaml/hardcaml.v0.17.1/opam |
Required by
- hardcaml-lua
- hardcaml_axi>=v0.17.0
- hardcaml_c>=v0.17.0
- hardcaml_circuits>=v0.17.0
- hardcaml_event_driven_sim
- hardcaml_fixed_point>=v0.17.0
- hardcaml_handshake>=v0.17.0
- hardcaml_of_verilog>=v0.17.0
- hardcaml_step_testbench>=v0.17.0
- hardcaml_verify>=v0.17.0
- hardcaml_verilator>=v0.17.0
- hardcaml_waveterm>=v0.17.0
- hardcaml_xilinx>=v0.17.0
- hardcaml_xilinx_components>=v0.17.0
- hardcaml_xilinx_reports>=v0.17.0
- ppx_hardcaml