hardcamlversion Documentation on ocaml.org

RTL Hardware Design in OCaml

Hardcaml is an embedded DSL for designing and simulating hardware in OCaml. Generic hardware designs are easily expressed using features such as higher order functions, lists, maps etc. A built in simulator allows designs to be simulated within Hardcaml. Designs are converted to either Verilog or VHDL to interact with standard back end tooling.

AuthorJane Street Group, LLC
LicenseMIT
Published
Homepagehttps://github.com/janestreet/hardcaml
Issue Trackerhttps://github.com/janestreet/hardcaml/issues
MaintainerJane Street developers
Availablearch != "arm32" & arch != "x86_32"
Dependencies
Source [http] https://github.com/janestreet/hardcaml/archive/refs/tags/v0.17.1.tar.gz
md5=7435ee8610c2205c5f912b4bf09163b0
sha512=38d7cf428bd3491024212e52776ac582183d7b5f6a494589a3697d9a213fa18347d6eeea23327859c340b0cb3b967c08cd21a8a7f8d15cf2de20e5598cb8456d
Edithttps://github.com/ocaml/opam-repository/tree/master/packages/hardcaml/hardcaml.v0.17.1/opam