hardcamlversion
RTL Hardware Design in OCaml
Hardcaml is an embedded DSL for designing and simulating hardware in OCaml. Generic hardware designs are easily expressed using features such as higher order functions, lists, maps etc. A built in simulator allows designs to be simulated within Hardcaml. Designs are converted to either Verilog or VHDL to interact with standard back end tooling.
Author | Jane Street Group, LLC |
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License | MIT |
Published | |
Homepage | https://github.com/janestreet/hardcaml |
Issue Tracker | https://github.com/janestreet/hardcaml/issues |
Maintainer | Jane Street developers |
Available | arch != "arm32" & arch != "x86_32" |
Dependencies |
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Source [http] | https://github.com/janestreet/hardcaml/archive/v0.14.1.tar.gz sha256=c18c14488da5759d3504c9a723086b99fe73c95871bd9c4de74ff032dd44b2fc md5=b05e14f646ad959aba2c4454d1cf143d |
Edit | https://github.com/ocaml/opam-repository/tree/master/packages/hardcaml/hardcaml.v0.14.1/opam |
Required by
- hardcaml-lua
- hardcaml_waveterm=v0.14.0
- ppx_deriving_hardcaml=v0.14.0