hardcamlversion
RTL Hardware Design in OCaml
Hardcaml is an embedded DSL for designing and simulating hardware in OCaml. Generic hardware designs are easily expressed using features such as higher order functions, lists, maps etc. A built in simulator allows designs to be simulated within Hardcaml. Designs are converted to either Verilog or VHDL to interact with standard back end tooling.
Author | Jane Street Group, LLC |
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License | MIT |
Published | |
Homepage | https://github.com/janestreet/hardcaml |
Issue Tracker | https://github.com/janestreet/hardcaml/issues |
Maintainer | Jane Street developers |
Dependencies |
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Source [http] | https://ocaml.janestreet.com/ocaml-core/v0.14/files/hardcaml-v0.14.0.tar.gz sha256=465e94af73a83517bff9880803d183fa5f1e6a41702cf27d44329c0c64ff6e1d md5=238d2dc37f029802217f883f64f7445d |
Edit | https://github.com/ocaml/opam-repository/tree/master/packages/hardcaml/hardcaml.v0.14.0/opam |
Required by
- hardcaml-lua
- hardcaml_waveterm=v0.14.0
- ppx_deriving_hardcaml=v0.14.0