hardcamlversion

RTL Hardware Design in OCaml

Hardcaml is an embedded DSL for designing and simulating hardware in OCaml. Generic hardware designs are easily expressed using features such as higher order functions, lists, maps etc. A built in simulator allows designs to be simulated within Hardcaml. Designs are converted to either Verilog or VHDL to interact with standard back end tooling.

AuthorJane Street Group, LLC
LicenseMIT
Published
Homepagehttps://github.com/janestreet/hardcaml
Issue Trackerhttps://github.com/janestreet/hardcaml/issues
MaintainerJane Street developers
Dependencies
Source [http] https://ocaml.janestreet.com/ocaml-core/v0.13/files/hardcaml-v0.13.0.tar.gz
sha256=9f7bb189c6de2bfb8d6bb060360148578e48e1d014c2c82bba48e18972bbbf5a
md5=692be272e1fee9515b3b0fd16f9a1a6d
Edithttps://github.com/ocaml/opam-repository/tree/master/packages/hardcaml/hardcaml.v0.13.0/opam