hardcamlversion
RTL Hardware Design in OCaml
Hardcaml is an embedded DSL for designing and simulating hardware in OCaml. Generic hardware designs are easily expressed using features such as higher order functions, lists, maps etc. A built in simulator allows designs to be simulated within Hardcaml. Designs are converted to either Verilog or VHDL to interact with standard back end tooling.
Author | Jane Street Group, LLC |
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License | MIT |
Published | |
Homepage | https://github.com/janestreet/hardcaml |
Issue Tracker | https://github.com/janestreet/hardcaml/issues |
Maintainer | Jane Street developers |
Dependencies | |
Source [http] | https://ocaml.janestreet.com/ocaml-core/v0.12/files/hardcaml-v0.12.0.tar.gz sha256=1bef834dd9105c26530600cd6a211727004af0741fe39376682fb833fda8b918 md5=bddd766d20ca9d90d3d4d0d521e0d2b2 |
Edit | https://github.com/ocaml/opam-repository/tree/master/packages/hardcaml/hardcaml.v0.12.0/opam |
Required by
- hardcaml-lua
- hardcaml_waveterm<v0.13.0
- ppx_deriving_hardcaml=v0.12.0